ArtSim innovative compute architecture provides sustainable speedup (20X minimum), comparing to any other SW solution. Furthermore, the architecture relaxes the silicon specification hence; old/cheap silicon process node can be utilized without affecting performance. At this point we have a prototype on FPGA and a demo that validate the technology. Next step is a scalable system on FPGA with minimal compiler support that can accommodate a beta customer design, this will be done in 1.5Y and will require 1.5M$. As for competition, it can come from the big 3 however, for many reasons, beyond the scope of this paper, historically; EDA companies’ gets totally new technologies by acquiring innovative startups. Typical exit valuation for major tool provider (like ArtSim) exceeds the 300M$ line.