70% of a chip project schedule is attributed to Design and Verification (aka front-end stage). Design/Verification engineer cycles through 3 phases - code/simulate/debug until design declared bug free. On the project level, regression tests consist of thousands of simulations running on thousands of servers must be executed before changes are committed to the data base. Clearly, simulation phase dominates project schedule, and as design size increase, so does the pain. Unfortunately Event Driven Simulation belongs to Graph Traversal problem class, as such, Cloud, GPGPU or any other naive parallelism does not help and often deteriorates run times. SW based logic simulation performance is no longer acceptable.